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165
XMEGA A [MANUAL]
8077I–AVR–11/2012
14.12.3 CTRLC – Control register C
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 3:0 – CMPx: Compare Output Value x
These bits allow direct access to the waveform generator's output compare value when the timer/counter is set in the
OFF state. This is used to set or clear the WG output value when the timer/counter is not running.
14.12.4 CTRLD – Control register D
Bit 7:5 – EVACT[2:0]: Event Action
These bits define the event action the timer will perform on an event according to Table 14-5 on page 165.
The EVSEL setting will decide which event source or sources have control in this case.
Table 14-5. Timer event action selection.
Selecting any of the capture event actions changes the behavior of the CCx registers and related status and control bits
to be used for capture. The error status flag (ERRIF) will indicate a buffer overflow in this configuration. See “Event
Action Controlled Operation” on page 155 for further details.
Bit 4 – EVDLY: Timer Delay Event
When this bit is set, the selected event source is delayed by one peripheral clock cycle. This is intended for 32-bit input
capture operation. Adding the event delay is necessary to compensate for the carry propagation delay when cascading
two counters via the event system.
Bit
7
654
32
10
+0x02
–
CMPD
CMPC
CMPB
CMPA
Read/Write
R
R/W
Initial Value
0
000
00
Bit
76543
210
+0x03
EVACT[2:0]
EVDLY
EVSEL[3:0]
Read/Write
R/W
Initial Value
00000
000
EVACT[2:0]
Group Configuration
Event Action
000
OFF
None
001
CAPT
Input capture
010
UPDOWN
Externally controlled up/ down count
011
QDEC
Quadrature decode
100
RESTART
Restart waveform period
101
FRQ
Frequency capture
110
PW
Pulse width capture
111
Reserved
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